High-Performance Systolic K-Way Merge Sorter Processor

A sorter system includes a clock continuously generating a series of clock signals, a systolic array circuit, and control circuitry in communication with serial access memory that stores data items of a sequence to be sorted and with the systolic array circuit to supply thereto data items as input and to receive therefrom data items as output. The systolic array circuit includes at least one processing module and K−1 registers, where K is an integer value greater than two. Each processing module has at least one of the registers, each register for storing one data item. The control circuitry serially presents K data items for input to the systolic array circuit in synchronization with the clock signals. On the next clock cycle after the control circuitry presents to the systolic array circuit the last of the K data items, the data item of least value in the given subsequence is output.